Non-volatile semiconductor memory cells using a floating gate to store charges thereon and memory arrays of such non-volatile memory cells formed in a semiconductor substrate are well known in the art. Typically, such floating gate memory cells have been of the split gate type, or stacked gate type, or a combination thereof.
One of the problems facing the manufacturability of semiconductor floating gate memory cell arrays has been the alignment of the various components such as source, drain, control gate, and floating gate. As the design rule of integration of semiconductor processing decreases, reducing the smallest lithographic feature, the need for precise alignment becomes more critical. Alignment of various parts also determines the yield of the manufacturing of the semiconductor products.
Self-alignment is well known in the art. Self-alignment refers to the act of processing one or more steps involving one or more materials such that the features are automatically aligned with respect to one another in that step processing. Accordingly, the present invention uses the technique of self-alignment to achieve the manufacturing of a semiconductor memory array of the floating gate memory cell type.
In the split-gate architecture, the control-gate FET is known to play a major role in disturbing mirror cells, as well as affecting the programming injection efficiency for source-side-injection FLASH cells. A good process control on the Lcg (also called the WL (word-line) poly length, which is the length of the control or select gate that is disposed over the channel) can ensure a full turn-off of the control-gate device, and hence can effectively prevent any disturbance in a mirror cell during programming (program disturb). The present invention is a method to realize a self aligned FLASH cell with improved full turn-off of the control-gate device with better program disturb characteristics. The present invention is also such a device.